Interface.37 9.4.2 Oscillator/Crystal Timing.37 9.4.3 MDC/MDIO Timing.38 9.4.4 MDIO Timing when OUTPUT STA.38 9.4.5 MDIO Timing when OUTPUT 9.4.6 100Base-TX Transmit Timing 9.4.7 100Base-TX Transmit Timing 9.4.8 100Base-TX Receive Timing Parameters.39 9.4.9 MII 100Base-TX Receive Timing Diagram.40 9.4.10 MII 10Base-T Nibble Transmit Timing Parameters.40 9.4.11 MII 10Base-T Nibble Transmit Timing Diagram.40 9.4.12 MII 10Base-T Receive Nibble Timing Parameters. ![]() DC and AC Electrical Characteristics 9.1 Absolute Maximum Ratings( ).36 9.2 Operating 9.3 DC Electrical 9.4 AC Electrical Characteristics & Timing Waveform. MII Register Description.23 8.1 Basic Mode Control Register (BMCR) 00.24 8.2 Basic Mode Status Register (BMSR) 01.25 8.3 PHY ID Identifier Register 02.26 8.4 PHY ID Identifier Register 03.26 8.5 Auto-negotiation Advertisement Register (ANAR) 04.27 8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) 0528 8.7 Auto-negotiation Expansion Register (ANER) 06.29 8.8 DAVICOM Specified Configuration Register (DSCR) 16.29 8.9 DAVICOM Specified Configuration and Status Register (DSCSR) 8.10 10Base-T Configuration / Status 18.32 8.11 DAVICOM Specified Interrupt Register 21.32 8.12 DAVICOM Specified Receive Error Counter Register (RECR) 22.33 8.13 DAVICOM Specified Disconnect Counter Register (DISCR) 23.33 8.14 DAVICOM Hardware Reset Latch State Register (RLSR) 9. Functional Description.13 7.1 MII Scrambler.16 7.2.1.3 Parallel to Serial Converter.16 7.2.1.4 NRZ to NRZI 7.2.1.7 4B5B Code Receiver.18 7.2.2.1 Signal Detect.18 7.2.2.2 Adaptive MLT-3 to NRZI Decoder.18 7.2.2.4 Clock Recovery Module.18 7.2.2.5 NRZI NRZ.18 7.2.2.6 Serial Descrambler.18 7.2.2.8 Code Group Operation.18 7.2.4 Collision Detection.19 7.2.5 Carrier Auto-Negotiation.19 7.2.7 MII Serial Management.20 7.2.8 Serial Management Interface.20 7.2.9 Management Interface Read Frame Structure.20 7.2.10 Management Interface Write Frame Structure.20 7.2.11 Power Reduced Mode.21 7.2.12 Power Down Mode.21 7.2.13 Reduced Transmit Power Mode.21 7.2.14 Feedback Vout and Vin for 5V.21 7.3 Auto MDIX Functional Description.22 8. LED Configuration.11 6.1 LED Functional Description.12 7. Pin Description.6 5.1 Normal MII Interface, pins.6 5.2 Media Interface, pins.8 5.3 LED Interface, pins.8 5.4 Mode, pins.8 5.5 Bias and Clock, pins.9 5.6 Power, pins.9 5.7 Table A (Media Type Selection).9 5.8 Pin Maps of Normal MII, Reduced MII, and 10Base-T GPSI (7-Wired) Mode. See sub_mdio_xfer_ex.10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiverġ. To access MDIO1 channel use sub_mdio_xfer_ex function with channel=1.īeginnig from FW version 0.3.2 and library version 0.1.12.24, SUB-20 supports CFP MSA compatible transactions at 4MHz MDC frequency. SUB-20 supports both MDIO frame formats defined in IEEE 802.3 Clause 22 and Clause 45.īeginning from FW version 0.2.8 and library version 0.1.12.18, additional MDIO1 channel is available on SPI header ( see SPI Header ). Status information is driven by the PHY synchronously with respect to MDC and is sampled synchronously by the SUB-20. Control information is driven by the SUB-20 synchronously with respect to MDC and is sampled synchronously by the PHY. ![]() ![]() MDIO is a bidirectional signal between PHY and the SUB-20 It is used to transfer control information and status between the PHY and the SUB-20. MDC is sourced by SUB-20 to the PHY as the timing reference for transfer of information on the MDIO signal. Where a PHY, or grouping of PHY's, is an individually manageable entity, known as an MDIO Manageable Device (MMD). It is two signal based interface between Station Management (SUB-20 in our case) and a Physical Layer device (PHY). MDIO is a Management Data Input/Output Interface defined in IEEE 802.3 Clause 22 and extended in Clause 45.
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